1. Field of the Invention
The invention relates generally to biasing the substrate of a semiconductor integrated circuit containing field effect devices, and more particularly, to a method of and apparatus for controlling substrate bias potential to prevent parasitic transistor latch up tending to occur in response to excessive power supply voltage.
2. Description of the Prior Art
A dynamic type semiconductor memory device has been well known. It is used as a main memory of a computer. FIG. 1 is a block diagram showing a whole structure of such conventional dynamic type semiconductor memory device.
Referring to FIG. 1, the dynamic type semiconductor memory device (hereinafter referred to as dynamic RAM) comprises a memory cell array including a plurality of memory cells serving as a memory portion, a row decoder and a column decoder for selecting the address thereof and an input/output interface portion including a sense amplifier connected to an input/output buffer. The plurality of memory cells are connected to each of the intersections of the word lines connected to the row decoder and the bit lines connected to the column decoder and these word lines and bit lines forming a matrix. Thus the said array is constituted.
Next the operation will be described. Upon receipt of the externally applied row address signal and column address signal, a memory cell is selected which is at the intersection of one word line and one bit line selected by the row decoder and the column decoder and the information is read from or written into the memory cell through the input/output interface portion including the sense amplifier and through the input/output buffer.
As to the further details of the operation of the Dynamic RAM, U.S. Pat. No. 3,940,747 entitled "High Density, High Speed Random Access Read-Write Memory" can be referred to.
Recently, the peripheral circuits at the dynamic RAM are formed of CMOS. The peripheral circuits comprise a clock generator circuit, a row and column address buffer, data in buffers and data out buffers shown in FIG. 1. The reason for this is that it decreases the power consumption of the dynamic RAM and it increases the speed of operation of the dynamic RAM. Meanwhile, a substrate voltage is applied to the substrate of the dynamic RAM, mainly for the following reasons. The first reason is that it decreases the bit line capacitance. The reason will be described in the following with reference to FIG. 2. FIG. 2 is a partial sectional view of a memory cell in a dynamic RAM. The memory cell comprises one transistor and one capacitor. The transistor comprises a source 51, a drain 52 and a gate electrode 53 which serves as a word line. The capacitor comprises a storage gate 54, an N.sup.+ diffusion layer 52 and an insulating film 55 interposed therebetween. A bit line 56 is connected to the N.sup.+ diffusion layer 51. Since the N.sup.+ diffusion layer 51 is formed on the main surface of the P type substrate, a PN junction is formed at the bit line connecting portion. Consequently, a junction capacitance is generated here. The junction capacitance varies dependent on a voltage applied to the PN junction portion. Therefore, the junction capacitance can be varied by applying a bias voltage to the substrate. The capacitance at the bit line connecting portion can be minimized, enabling fast operation of the dynamic RAM.
Meanwhile, the read out voltage from the memory cell V.sub.R can be represented by the following equation. ##EQU1## where
C.sub.B : bit line capacitance
C.sub.S : storage capacitance
V.sub.CC : supply voltage For the above described reasons, when a substrate bias voltage is applied, the capacitance C.sub.B is decreased. Therefore, the ratio of C.sub.B /C.sub.S can be improved, increasing the signal voltage of the read out voltage from the cell.
The second reason is that it adjusts the threshold voltage of the transfer gate of the memory cell. The reason will be described in the following with reference to FIG. 3. FIG. 3 shows the relation between the substrate bias voltage and the threshold voltage of the MOS transistor. As shown in the figure, the threshold voltage of the MOS transistor depends on the substrate voltage. When the substrate voltage is small (the portion A in the figure) the threshold voltage fluctuates widely, and when it is large (the portion B in the figure), the fluctuation of the threshold voltage varies small even if the amount of fluctuation of the substrate voltage is the same (V.sub.A &gt;V.sub.B). It is not preferable to the operation of the dynamic RAM that the threshold voltage varies widely due to a slight fluctuation of the substrate potential. Therefore, it is necessary that the MOS transistor is operated in the region where the fluctuation V.sub.BB have little influence on the fluctuation of V.sub.TH.
The third reason is that it prevents minority carriers from being injected when the signal is externally inputted. When electrons are injected in the substrate, the electrons are trapped in a capacitor (the reference numeral 52 of FIG. 2) when no substrate bias voltage is supplied to the substrate. Consequently, the stored information in the memory cell are destroyed. If a substrate bias voltage of about -3 V is applied to the substrate, the electrons injected into the substrate can be trapped at the supply potential.
FIG. 4 is a cross sectional view of a CMOS inverter which is often employed in a peripheral circuit of the dynamic RAM. The CMOS inverter comprises an N channel transistor formed on a main surface of a P type substrate 32 and a P channel transistor formed on a main surface of an N well 28. The N channel transistor comprises two N.sup.+ diffusion layers 23 and 24, and a gate electrode 27 formed above and insulated from the channel region, the end of which is defined by the N.sup.+ diffusion layers 23 and 24. The P channel transistor, formed on the main surface of the N well 28, comprises two P.sup.+ diffusion layers 21 and 22 and a gate electrode 26 formed above and insulated from the channel region, the end of which is defined by the P.sup.+ diffusion layers 21 and 22. The N channel transistor and the P channel transistor are separated from each other on the main surface of the substrate 32 by an oxide film 29. A supply voltage V.sub.CC is connected to the N.sup.+ diffusion layer 25 and to the P.sup.+ diffusion layer 21 formed on the main surface of the N well 28. One of the N.sup.+ diffusion layers 24 constituting the N channel transistor is grounded. The gate electrodes 26 and 27 are connected to an input line of the inverter, and the P.sup.+ diffusion layer 22 and the N.sup.+ diffusion layer 23 are connected to an output line of the inverter. A vertical PNP transistor 30 and a lateral NPN transistor are parasitic upon the inverter. The reason for this is that the N well 28 is formed on the P type substrate 32. A substrate voltage V.sub.BB is applied to the substrate 32.
FIG. 5 shows a conventionally used substrate voltage V.sub.BB generation circuit. This is shown in "Static and Transient Latch up Hardness in N-Well MOS with on-chip Substrate Bias Generator" D. Takacs, et al., IEDM 85, 1985. Referring to FIG. 3, the substrate voltage generation circuit comprises an oscillator 4 to which the supply voltage V.sub.CC is applied, a capacitor 3 having one electrode connected to the oscillator 4, a first MOS transistor 1 having its gate electrode and source connected to the other electrode of the capacitor 3, and a second MOS transistor having its drain connected to the source of the first MOS transistor 1 at a node 5 and its gate electrode and source connected to the substrate.
The operation of the conventional substrate voltage generation circuit will be described. When the oscillator 4 oscillates at 5 MHz and the voltage of V.sub.CC, the potential of the node 5 becomes the threshold voltage V.sub.TH of the MOS transistor. The reason for this is that when V.sub.CC exceeds the threshold voltage V.sub.TH of the first MOS transistor 1, the node 5 is grounded by the switching function of the first MOS transistor 1. On this occasion, the second MOS transistor 2 is in the cut off state. When the voltage of the oscillator changes from V.sub.CC to 0, the potential of the node 5 tends to become V.sub.TH - V.sub.CC. However, on this occasion, the second MOS transistor 2 turns on and electrons flow into the node 5 from V.sub.BB. Consequently, the potential of V.sub.BB slightly lowers. By the repetition of the above described operation, the potential of V.sub.BB gradually becomes negative potential. The above described operation is the well known charge pump function and the detail thereof is shown in, e.g., "A 70-ns 1k MOS RAM" R. D. Pashley and G. A. McCormick, ISSC Digest of Technical Papers, pp. 138-139, Feb., 1976.
FIG. 6 shows the dependency of the supply voltage (V.sub.CC) of the substrate voltage generation circuit of FIG. 3. The solid line a shows the standby state while the dotted line b shows the operating state. When the supply voltage V.sub.CC becomes high, the high level of the output of the oscillator 4 also becomes high. As a result, the substrate voltage V.sub.BB becomes deep in the negative potential direction. As is shown in "Single 5-V, 65k RAM with Scaled-Down MOS Structure" Hiroo Masuda et al., IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, pp. 1607-1612, Aug., 1980. The substrate potential becomes shallow in the operating state. The reason is that the substrate current flows and the charge pump can not cope with this current. Consequently, sometimes the substrate potential becomes positive potential due to the high resistance of the substrate. Meanwhile, since the substrate current does not flow in the standby state, the substrate potential remains in the deep state up to a high supply voltage V.sub.CC. In the standby state, however, sometimes the substrate becomes a positive potential due to a junction breakdown of the N.sup.+ diffusion layer and the substrate of the supply potential.
When the substrate becomes the positive potential as described above, a latch up phenomenon occurs. The latch up phenomenon in the CMOS structure is well known. The latch up occurs with the bipolar transistors 30 and 31 of FIG. 2 being turned on. The major causes of the latch up are as follows.
(1) Causes in the normal operation
.circle.1 Instant power failure
.circle.2 Failure of the power supply of the dynamic RAM
.circle.3 Generation of surge voltage
(2) Accelerated test
A supply voltage exceeding a specified value is applied to the DRAM on purpose to screen defective DRAMs. When the latch up occurs, a current of some 10 to some 100 mA flows between the supply voltage V.sub.CC and the ground, the wiring materials melt causing the destruction of the device.